Theoretical Computer Science
A calculus of broadcasting systems
ESOP '94 Selected papers of ESOP '94, the 5th European symposium on Programming
Triggered message sequence charts
Proceedings of the 10th ACM SIGSOFT symposium on Foundations of software engineering
Verification of a Radio-Based Signaling System Using the STATEMATE Verification Environment
Formal Methods in System Design
Automatic verification of real-time communicating systems by constraint-solving
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Smart Play-out of Behavioral Requirements
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Model Checking via Reachability Testing for Timed Automata
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
An Automata Based Interpretation of Live Sequence Charts
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
LSCs: Breathing Life into Message Sequence Charts
Proceedings of the IFIP TC6/WG6.1 Third International Conference on Formal Methods for Open Object-Based Distributed Systems (FMOODS)
Formal Verification of a Power Controller Using the Real-Time Model Checker UPPAAL
ARTS '99 Proceedings of the 5th International AMAST Workshop on Formal Methods for Real-Time and Probabilistic Systems
Scenario-Based Monitoring and Testing of Real-Time UML Models
«UML» '01 Proceedings of the 4th International Conference on The Unified Modeling Language, Modeling Languages, Concepts, and Tools
Come, Let's Play: Scenario-Based Programming Using LSC's and the Play-Engine
Come, Let's Play: Scenario-Based Programming Using LSC's and the Play-Engine
The Rhapsody UML Verification Environment
SEFM '04 Proceedings of the Software Engineering and Formal Methods, Second International Conference
Model Checking Live Sequence Charts
ICECCS '05 Proceedings of the 10th IEEE International Conference on Engineering of Complex Computer Systems
International Journal on Software Tools for Technology Transfer (STTT) - Special section on high-level test of complex systems
Verifying Real-Time Systems against Scenario-Based Requirements
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Timed sequence diagrams and tool-based analysis: a case study
UML'99 Proceedings of the 2nd international conference on The unified modeling language: beyond the standard
On the expressive power of live sequence charts
Program analysis and compilation, theory and practice
Scenario-based analysis and synthesis of real-time systems using UPPAAL
Proceedings of the Conference on Design, Automation and Test in Europe
Check it out: on the efficient formal verification of live sequence charts
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Temporal logic for scenario-based specifications
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Efficient scenario verification for hybrid automata
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Proving and explaining the unfeasibility of message sequence charts for hybrid systems
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
SMT-based scenario verification for hybrid systems
Formal Methods in System Design
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This article proposes two approaches to tool-supported automatic verification of dense real-time systems against scenario-based requirements, where a system is modeled as a network of timed automata (TAs) or as a set of driving live sequence charts (LSCs), and a requirement is specified as a separate monitored LSC chart.We make timed extensions to a kernel subset of the LSC language and define a trace-based semantics. By translating a monitored LSC chart to a behavior-equivalent observer TA and then non-intrusively composing this observer with the original TA-modeled real-time system, the problems of scenario-based verification reduce to computation tree logic (CTL) real-time model checking problems. When the real-time system is modeled as a set of driving LSC charts, we translate these driving charts and the monitored chart into a behavior-equivalent network of TAs by using a "one-TA-per-instance line" approach, and then reduce the problems of scenario-based verification also to CTL real-time model checking problems. We show how we exploit the expressivity of the TA formalism and the CTL query language of the real-time model checker Uppaal to accomplish these tasks. The proposed two approaches are implemented in the Uppaal tool and built as a tool chain, respectively. We carry out a number of experiments with both verification approaches, and the results indicate that these methods are viable, computationally feasible, and the tools are effective.