Theoretical Computer Science
LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
Triggered message sequence charts
Proceedings of the 10th ACM SIGSOFT symposium on Foundations of software engineering
An Automata Based Interpretation of Live Sequence Charts
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Come, Let's Play: Scenario-Based Programming Using LSC's and the Play-Engine
Come, Let's Play: Scenario-Based Programming Using LSC's and the Play-Engine
Timed sequence diagrams and tool-based analysis: a case study
UML'99 Proceedings of the 2nd international conference on The unified modeling language: beyond the standard
On the expressive power of live sequence charts
Program analysis and compilation, theory and practice
Temporal logic for scenario-based specifications
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Scenario-based verification of real-time systems using Uppaal
Formal Methods in System Design
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We propose an approach to automatic verification of real-time systems against scenario-based requirements. A real-time system is modeled as a network of Timed Automata (TA), and a scenario-based requirement is specified as a Live Sequence Chart (LSC). We define a trace-based semantics for a kernel subset of the LSC language. By equivalently translating an LSC chart into an observer TA and then non-intrusively composing this observer with the original system model, the problem of verifying a real-time system against a scenario-based requirement reduces to a classical real-time model checking problem. We show how this is accomplished in the context of the Uppaal model checker.