Live sequence charts applied to hardware requirements specification and verification: A VCI bus interface model

  • Authors:

  • Annette Bunker;Ganesh Gopalakrishnan;Konrad Slind

  • Affiliations:

  • School of Computing, University of Utah, 84112, Salt Lake City, Utah, USA and Electrical and Computer Engineering Department, Utah State University, 84322, Logan, Utah, USA;School of Computing, University of Utah, 84112, Salt Lake City, Utah, USA;School of Computing, University of Utah, 84112, Salt Lake City, Utah, USA

  • Venue:
  • International Journal on Software Tools for Technology Transfer (STTT) - Special section on high-level test of complex systems
  • Year:
  • 2005

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Abstract

Techniques and tools for formally verifying compliance with industry standards are important, especially in System-on-Chip (SoC) designs: a failure to integrate externally developed intellectual property (IP) cores is prohibitively costly. There are three essential components in the practical verification of compliance with a standard. First, an easy-to-read and yet formal specification of the standard is needed; we propose Live Sequence Charts (LSCs) as a high-level visual notation for writing specifications. Second, assertions should be generated directly from the specification; an implementation will be scrutinized, usually by model checking, to check that it satisfies each assertion. Third, a formal link must be made between proofs of assertions and compliance with the original specification. As an example, we take the Virtual Component Interface (VCI) Standard. We compare three efforts in verifying that the same register transfer level code is VCI-compliant. The first two efforts were manual, while the third used a tool, lscAssert, to automatically generate assertions in LTL. We discuss the details of the assertion generation algorithm.