Handbook of theoretical computer science (vol. B)
Tree automata, Mu-Calculus and determinacy
SFCS '91 Proceedings of the 32nd annual symposium on Foundations of computer science
Memory-efficient algorithms for the verification of temporal properties
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reasoning about infinite computations
Information and Computation
An automata-theoretic approach to linear temporal logic
Proceedings of the VIII Banff Higher order workshop conference on Logics for concurrency : structure versus automata: structure versus automata
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Symbolic Model Checking
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
Fair Simulation Relations, Parity Games, and State Space Reduction for Büchi Automata
ICALP '01 Proceedings of the 28th International Colloquium on Automata, Languages and Programming,
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Small Progress Measures for Solving Parity Games
STACS '00 Proceedings of the 17th Annual Symposium on Theoretical Aspects of Computer Science
CONCUR '97 Proceedings of the 8th International Conference on Concurrency Theory
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Fast LTL to Büchi Automata Translation
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Checking for Language Inclusion Using Simulation Preorders
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
An algebraic definition of simulation between programs
IJCAI'71 Proceedings of the 2nd international joint conference on Artificial intelligence
Bridging the gap between fair simulation and trace inclusion
Information and Computation
Theories of automata on ω-tapes: A simplified approach
Journal of Computer and System Sciences
Safraless compositional synthesis
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Büchi automata can have smaller quotients
ICALP'11 Proceedings of the 38th international conference on Automata, languages and programming - Volume Part II
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
Advanced automata minimization
POPL '13 Proceedings of the 40th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Synthesizing nonanomalous event-based controllers for liveness goals
ACM Transactions on Software Engineering and Methodology (TOSEM)
| Hi-index | 0.00 |
We consider the problem of minimization of generalized Büchi automata. We extend fair-simulation minimization and delayed-simulation minimization to the case where the Büchi automaton has multiple acceptance conditions. For fair simulation, we show how to efficiently compute the fair-simulation relation while maintaining the structure of the automaton. We then use the fair-simulation relation to merge states and remove transitions. Our fair-simulation algorithm works in time O(mn3k2) where m is the number of transitions, n is the number of states, and k is the number of acceptance sets. For delayed simulation, we extend the existing definition to the case of multiple acceptance conditions. We show that our definition can indeed be used for minimization and give an algorithm that computes the delayed-simulation relation. Our delayed-simulation algorithm works in time O(mn3k). We implemented the two algorithms and report on experimental results.