Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
Logic synthesis
Easily Testable Realizations for Generalized Reed-Muller Expressions
IEEE Transactions on Computers
An Algorithm for the Multi-Level Minimazation of Reed-Muller Rpresentations
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
IBM Journal of Research and Development - Mathematics and computing
A Method for Modulo-2 Minimization
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
Minimization of OR-XNOR expressions using four new linking rules
AIKED'08 Proceedings of the 7th WSEAS International Conference on Artificial intelligence, knowledge engineering and data bases
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This paper introduces the fundamental theory, algorithms, and terminology regarding synthesis of multi-level Dual Reed-Muller expressions. The increasing interest in using Dual Reed-Muller expressions as a way of representing and manipulating switching functions, and as a mean of designing circuits based on OR/XNOR gates has led to this research. Up to present there are only two-level Dual Reed-Muller minimization algorithms in use, although the need for multi-level minimization algorithms has been recognized. A new theory and algorithms for multi-level Dual Reed-Muller minimization have been developed. It introduces a Dual Reed-Muller factored form and uses algebraic algorithms for factorization decomposition, re-substitution, and extraction of common cubes and subexpressions.