The essence of logic circuits
Computer aided logical design with emphasis on VLSI (4th ed.)
Computer aided logical design with emphasis on VLSI (4th ed.)
Digital design: principles and practices (2nd ed.)
Digital design: principles and practices (2nd ed.)
Fundamentals of Logic Design
Logic Design and Switching Theory
Logic Design and Switching Theory
Discrete Mathematical Structures
Discrete Mathematical Structures
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Introduction to Switching Theory and Logical Design
Introduction to Switching Theory and Logical Design
Fundamentals of Digital Logic with VERILOG Design
Fundamentals of Digital Logic with VERILOG Design
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A pedagogical treatment of two-level multiple-output logic minimization is presented through a compact exposition of a novel manual fast procedure. This procedure is a purely map technique which generalizes the map procedure for single-output minimization. It requires neither the generation of the set of all paramount prime implicants, nor the construction of a cover matrix. Instead, it utilizes certain visual interactions between various groups of maps placed at distinct levels of a Hasse diagram, which is conveniently drawn in a Karnaugh map layout so that any parent map is easily visualized as adjacent to all its children maps. The present exposition is believed to enhance what is currently available in undergraduate texts, and is intended as a supplement to, rather than a replacement of, automated computational experience. An illustrative example demonstrates the proposed procedure for the dual cases of AND-OR and OR-AND minimizations.