Generalized SAT-sweeping for post-mapping optimization
Proceedings of the 49th Annual Design Automation Conference
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A method for optimizing digital logic networks is described. This approach uses the techniques of global flow analysis to efficiently gather information about the relationship between different wires in a circuit and uses methods from network flow to use this information to optimize the circuit. It differs from earlier methods for optimization of multilevel logic networks in that valid rearrangements of signal connections depend on the maintenance of global circuit invariants. An algorithm which reduces the problem of finding small circuits in this equivalence class to the problem of finding a min-cut in an associated graph is described. This algorithm has been implemented and forms part of an automatic design system in use within IBM. The authors describe the results of experiments undertaken to evaluate the effect of the techniques