A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator

Authors:
Fumiyasu Hirose;Koichiro Takayama;Nobuaki Kawato
Affiliations:
Fujitsu Laboratories ltd.;Fujitsu Laboratories ltd.;Fujitsu Laboratories ltd.
Venue:
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Year:
1988

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Abstract

We synthesize a test-generation circuit S(C,F) which is a combination of the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test pattems are generated by searching the inputs to expose faults at the outputs using an ultrahigh-speed simulator (SP).