Test Synthesis with Alternative Graphs
IEEE Design & Test
Test Cost Minimization for Hybrid Bist
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Polynomially Complete Fault Detection Problems
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Project verification and construction of superchip tests at the RTL level
Automation and Remote Control
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The state-of-the-art in testing of the very large scale integrated (VLSI) circuits was analyzed. Consideration was given to the directed construction of tests at the system level of presentation of the object or the register transfer level in the VHDL language. The class of functional faults considered at the directed construction of a test corresponds to the bit-stuck faults of the VLSI circuit realizations with the elements of the corresponding design libraries. Proposed was a method of directed test design enabling one at the earlier stages of design to analyze testability vs. the technological design libraries used.