Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Design for Test: For Digital Integrated Circuits
Design for Test: For Digital Integrated Circuits
Application of partial-response channel coding to magnetic recording systems
IBM Journal of Research and Development
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PRML (Partial Response Maximum Likelihood)read channel devices are heterogeneous, complex,mixed signal devices. This paper describesmethodology for testing a state-of-the-art CMOS readchannel, including Design-for-Test (DfT) techniques,Device-Interface-Board (DIB) design features and testflow. DfT techniques such as scan, Built-In Self-Test(BIST) loop-back and ad-hoc analog test features arediscussed. Analog test grading methods (Test-for-Quality or TFQ) are also presented. Afterwards a briefoverview of the DIB hardware highlighting criticalfeatures such as wide band analog and high speeddigital undersampling tester interfaces are reviewed.An overview of the test suite defining the mix offunctional, structured, IDDQ and BIST tests is offered.The problems and possible solutions of embedding aPRML channel into a System-on-Chip are alsoextensively explored.