Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Bridge fault simulation strategies for CMOS integrated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Residual Charge on the Faulty Floating Gate MOS Transistor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On Accurate Modeling and Efficient Simulation of CMOS Opens
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An unexpected factor in testing for CMOS opens: the die surface
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Charge-based fault simulation for CMOS network breaks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Current testability analysis of feedback bridging faults in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Shorts and opens are the most common types of defects in today's CMOS ICs. In this paper we show forthe first time that an open in the interconnect wiringof a digital CMOS circuit can cause oscillation or sequential behavior. We also analyze and compare thefactors affecting the probabilities for an interconnectopen and a feedback bridging fault to oscillate or display sequential behavior.