Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Peak power estimation of VLSI circuits: new peak power measures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Challenges of High Supply Currents During VLSI Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-outs
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Circuit and Platform Design Challenges in Technologies beyond 90nm
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Pattern Generation and Estimation for Power Supply Noise Analysis
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Test Pattern Generation for Power Supply Droop Faults
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Journal of Electronic Testing: Theory and Applications
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Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause a sudden drop or rise in power supply voltage. This change is known as power droop and is an instance of power supply noise. Although power droop can cause an IC to fail, such failures cannot currently be screened during testing because they are not covered by conventional fault models. This article presents a technique for screening such failures. The authors propose a heuristic method to generate test sequences that create worst-case power drop by accumulating the high- and low-frequency effects. The authors employ a dynamically constrained version of the classical D-algorithm, which generates new constraints on the fly, for test generation. The obtained patterns can be used for manufacturing testing as well as for early silicon validation. The authors have implemented a prototype ATPG to demonstrate the feasibility of this approach, and they generate test sequences for ISCAS circuits.