Post-layout optimization of power and timing for ECL LSIs

Authors:
A. Onozawa;H. Kitazawa;K. Kawai
Affiliations:
NTT LSI Laboratories, Atsugi, Kanagawa 243-O1, Japan;NTT R&D Headquarters, Chiyodaku, Tokyo 100, Japan;NTT LSI Laboratories, Atsugi, Kanagawa 243-01, Japan
Venue:
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Year:
1995

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Abstract