A view of a user-oriented production test data generation system
DAC '70 Proceedings of the 7th Design Automation Workshop
Prediction of wiring space requirements for LSI
DAC '77 Proceedings of the 14th Design Automation Conference
The chip layout problem: An automatic wiring procedure
DAC '77 Proceedings of the 14th Design Automation Conference
Unified Shapes Checker - a checking tool for LSI
DAC '79 Proceedings of the 16th Design Automation Conference
Post-layout optimization of power and timing for ECL LSIs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
IBM FSD VLSI chip design methodology
DAC '83 Proceedings of the 20th Design Automation Conference
An interactive system for VLSI chip physical design
IBM Journal of Research and Development
| Hi-index | 0.00 |
This paper describes a design system capable of designing chips in the range of 5K to 7K equivalent three-way NOR gates. A key feature of the system is the ability to design chips with large macros (RAMs and PLAs). This design system is part of IBM's corporate-wide Engineering Design System (EDS). EDS provides the capabilities of logic simulation, automatic placement and wiring, checking, and test pattern generation (I). This paper describes the key capabilities of the system, specifically as applied to IBM's silicon gate process. Topics covered include a description of the chip image and circuits, the automatic generation of large macros, the automatic placement and interconnection of circuits and macros, and a delay calculator/optimizer.