Timing uncertainty analysis for time-of-flight systems

Authors:
John R. Feehrer;Harry F. Jordan
Affiliations:
Optoelectronic Computing Systems Center, Campus Box 525, University of Colorado, Boulder, CO;Optoelectronic Computing Systems Center, Campus Box 525, University of Colorado, Boulder, CO
Venue:
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Year:
1994

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Abstract

Time-of-flight synchronization is a new digital design methodology that eliminates all latching devices, allowing higher clock rates than alternative timing schemes. Synchronization is accomplished by precisely balancing connection delays. Many effective pipeline stages are created by pipelining combinational logic, similar in concept to wave pipelining but differing in several respects. Due to the unique flow-through nature of circuits and to the need for pulse-mode operation, time-of-flight design exposes interesting new areas for CAD timing analysis. This paper discusses how static propagation delay uncertainty limits the clock period for time-of-flight circuits built with opto-electronic devices. We present algorithms for placing a minimum set of clock gates to restore timing in feedback loops that implement memory and for propagating delay uncertainty through a circuit graph. A mixed integer program determining the minimum feasible clock period subject to pulse width and arrival time constraints is discussed. Algorithms are implemented in XHatch, a time-of-flight CAD package.