Design and implementation of a prototype optical deflection network

  • Authors:

  • John Feehrer;Jon Sauer;Lars Ramfelt

  • Affiliations:

  • Optoelectronic Computing Systems Center, University of Colorado Boulder, CO;Optoelectronic Computing Systems Center, University of Colorado Boulder, CO;Department of Teleinformatics, Royal Institute of Technology, Stockholm, Sweden

  • Venue:
  • SIGCOMM '94 Proceedings of the conference on Communications architectures, protocols and applications
  • Year:
  • 1994

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Abstract

We describe the design and implementation of a packet-switched fiber optic interconnect prototype with a ShuffleNet topology, intended for use in shared-memory multiprocessors. Coupled with existing latency-hiding mechanisms, it can reduce latency to remote memory locations. Nodes use deflection routing to resolve contention. Each node contains a processor, memory, photonic switch, and packet routing processor. Payload remains in optical form from source to final destination. Each host processor is a commercial workstation with FIFO interfaces between its bus and the photonic switch. A global clock is distributed optically to each node to minimize skew. Component costs and network performance figures are presented for various node configurations including bit-per-wavelength and fiber-parallel packet formats. Our efforts to implement and test a practical interconnect including real host computers distinguishes our work from previous theoretical and experimental work. We summarize obstacles we encountered and discuss future work.