Certified timing verification and the transition delay of a logic circuit

Authors:
Srinivas Devadas;Kurt Keutzer;Sharad Malik;Albert Wang
Affiliations:
Department of EECS, Massachusetts Institute of Technology, Cambridge, MA;Synopsys, Inc., Mountain View, CA;Department of Electronic Engineering, Princeton University, Princeton, NJ;Synopsys, Inc., Mountain View, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1994

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Abstract

Most research in timing verification has implicitly assumed a single vector floatins mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to cemB static timing verification.