Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Path sensitization of combinational circuits and its impact on clocking of sequential systems
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Certified timing verification and the transition delay of a logic circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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