Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Coping with RC(L) interconnect design headaches
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
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This paper presents a technique for transistor-level timing simulation of MOS circuits driving RC interconnect loads. The RC interconnect is represented as a reduced-order model (e.g. /spl pi/-model). An effective capacitance is analytically derived from the reduced-order model by local linearization of the MOS devices in the driver circuit and is dynamically updated as the output voltage and regions of operation of the MOS devices in the driver circuit change. The effective capacitance is then applied as a load to the driver circuit and the output waveform is obtained by analytically solving the nonlinear state equation of the driving node. Extensive simulation results under various loading conditions and input transition times are provided to demonstrate the accuracy and efficiency of this technique.