DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Preservation of passivity during RLC network reduction via split congruence transformations
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Analysis of interconnect networks using complex frequency hopping (CFH)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multipoint moment matching model for multiport distributed interconnect networks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Error bounded Padé approximation via bilinear conformal transformation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model-reduction of nonlinear circuits using Krylov-space techniques
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interconnect analysis: from 3-D structures to circuit models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Passive model order reduction of multiport distributed interconnects
Proceedings of the 37th Annual Design Automation Conference
Practical considerations for passive reduction of RLC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Model reduction for DC solution of large nonlinear circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial
Analog Integrated Circuits and Signal Processing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
System Level Modeling of Microsystems Using Order Reduction Methods
Analog Integrated Circuits and Signal Processing
Poor Man's TBR: A Simple Model Reduction Scheme
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Structure preserving reduction of frequency-dependent interconnect
Proceedings of the 42nd annual Design Automation Conference
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques
Proceedings of the 46th Annual Design Automation Conference
HORUS - high-dimensional model order reduction via low moment-matching upgraded sampling
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic stability checking for large linear analog integrated circuits
Proceedings of the 48th Design Automation Conference
Model order reduction of fully parameterized systems by recursive least square optimization
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Recent work in the area of model-order reduction for RLC interconnect networks has been focused on building reduced-order models that preserve the circuit-theoretic properties of the network, such as stability, passivity, and synthesizability. Passivity is the one circuit-theoretic property that is vital for the successful simulation of a large circuit netlist containing reduced-order models of its interconnect networks. Non-passive reduced-order models may lead to instabilities even if they are themselves stable. In this paper, we address the problem of guaranteeing the accuracy and passivity of reduced-order models of multiport RLC networks at any finite number of expansion points. The novel passivity-preserving model-order reduction scheme is a block version of the rational Arnoldi algorithm. The scheme reduces to that of the PRIMA algorithm when applied to a single expansion point at zero frequency. Although the treatment of this paper is restricted to expansion points that are on the negative real axis, it is shown that the resulting passive reduced-order model is superior in accuracy to the one that would result from expanding the original model around a single point. Nyquist plots are used to illustrate both the passivity and the accuracy of the reduced-order models.