A scalable power modeling approach for embedded memory using LIB format

Authors:
Wen-Tsan Hsieh;Chi-Chia Yu;Chien-Nan Jimmy Liu;Yi-Fang Chiu
Affiliations:
Dept. of Electrical Engineering National Central University, Jhongli, Taoyuan, Taiwan, R.O.C.;Dept. of Electrical Engineering National Central University, Jhongli, Taoyuan, Taiwan, R.O.C.;Dept. of Electrical Engineering National Central University, Jhongli, Taoyuan, Taiwan, R.O.C.;Industrial Technological Research Institute, Chutung, Hsinchu, Taiwan, R.O.C.
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

In this work, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effect and the scaling factors that use the information of physical architecture. The proposed approach is very useful to be combined with memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the proposed dummy modular approach can link our enhanced memory power model into commercial power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.