High-performance routing trees with identified critical sinks
DAC '93 Proceedings of the 30th international Design Automation Conference
Modern heuristic techniques for combinatorial problems
Modern heuristic techniques for combinatorial problems
Behavioral network graph: unifying the domains of high-level and logic synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Unifying behavioral synthesis and physical design
Proceedings of the 37th Annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Cone Based Clustering for List Scheduling Algorithms
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Specification and design-space exploration for high-level synthesis of analog and mixed-signal systems
Modeling digital substrate noise injection in mixed-signal IC's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
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This paper presents a CAD methodology and a tool for high-level synthesis (HLS) of digital hardware for mixed analog-digital chips. In contrast to HLS for digital applications, HLS for mixed-signal systems is mainly challenged by constraints, such as digital switching noise (DSN), that are due to the analog circuits. This paper discusses an integrated approach to HLS and power net routing for effectively reducing DSN. Motivation for this research is that HLS has a high impact on DSN reduction, however, DSN evaluation is very difficult at a high level. Integrated approach also employs an original method for fast evaluation of DSN and an algorithm for power net routing and sizing. Experiments showed that our combined binding and scheduling method produces better results than traditional HLS techniques. Finally, DSN evaluation using the proposed algorithm can be significantly faster than SPICE simulation.