Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Interval scheduling: fine-grained code scheduling for embedded systems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesis of software programs for embedded control application
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Conflict modelling and instruction scheduling in code generation for in-house DSP cores
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Scalable performance scheduling for hardware-software cosynthesis
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
CodeSyn: a retargetable code synthesis system (abstract)
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
Constrained software generation for hardware-software systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
A model for system-level timed analysis and profiling
Proceedings of the conference on Design, automation and test in Europe
High-level architectural co-simulation using Esterel and C
Proceedings of the ninth international symposium on Hardware/software codesign
Verification strategy for integration 3G baseband SoC
Proceedings of the 40th annual Design Automation Conference
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The application range of embedded computing is going to cover the majority of market products spanning from consumer electronic, automotive, telecom and process control. For such applications, typically there is strong cooperation between dedicated hardware modules and software systems. An important issue toward a fully automated system-level implementation is represented by the software development process. The basic requirements are: accurate timing characterization to be used during the early stages of the design to compare alternative architectures and reliable synthesis techniques to ensure the respect of the correct functionality by avoiding, as much as possible, the direct designer's intervention during the development process. This paper describes a novel methodology to address the needs of concurrently synthesizing the software component of a control-dominated hardware-software system, possibly under real-time constraints. An intermediate model (Virtual Instruction Set) for the software is presented, suitable for both for synthesis and analysis purposes. The overall system synthesis is presented with particular emphasis on the problem of low level performance estimation, static scheduling of the software process and retargetable code synthesis.