The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Efficient software performance estimation methods for hardware/software codesign
DAC '96 Proceedings of the 33rd annual Design Automation Conference
CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
The use of a virtual instruction set for the software synthesis of Hw/Sw embedded systems
ISSS '96 Proceedings of the 9th international symposium on System synthesis
A timing-accurate modeling and simulation environment for networked embedded systems
Proceedings of the 40th annual Design Automation Conference
TTool for DIPLODOCUS: an environment for design space exploration
NOTERE '08 Proceedings of the 8th international conference on New technologies in distributed systems
Rewriting logic based performance estimation of embedded systems
ASMTA'10 Proceedings of the 17th international conference on Analytical and stochastic modeling techniques and applications
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
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This paper introduces an architectural simulation environment, aimed at defining the best SOC architecture for complex system-level applications. The application is modeled using an abstract Timing Modeling Language, that describes the requests (e.g., memory accesses, I/Os, etc.) that the application makes to the architecture. The abstract architecture is modeled at the cycle-accurate level using a mixture of Esterel (a synchronous language) and C. We discuss the results of the application of this tool to a GSM/GPRS application, including a dramatic speed-up of the architectural exploration phase.