High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Predicting deterministic execution times of real-time programs
Predicting deterministic execution times of real-time programs
Specification and design of embedded systems
Specification and design of embedded systems
Software scheduling in the co-synthesis of reactive real-time systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesis of software programs for embedded control application
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A co-synthesis approach to embedded system design automation
Design Automation for Embedded Systems
Operating system principles
Code Generation for Embedded Processors
Code Generation for Embedded Processors
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We consider the problem of generation of embedded software from input system descriptions in a hardware description language (HDL). Generation of software for embedded computing requires a total ordering of operations, or linearization, under constraints to ensure timely interaction with other system components. We show by example conditions where no ordering of operations in a HDL can produce the modeled functionality in software. Therefore, the existence condition for software generation, or serializability, must be ensured before attempting any linearization. We present the conditions based on variable definition and use analysis under which operation linearization is possible. We then present our approach to operation serialization under timing constraints to produce efficient schedules for the embedded software.