A novel parallel parity checksum generator complying with ITU-T J.83 annex B

Authors:
Eonpyo Hong;Eungu Jung;Dongsoo Har;Jaewon Yim
Affiliations:
Gwangju Institute of Science and Technology, Gwangju, Republic of Korea;Gwangju Institute of Science and Technology, Gwangju, Republic of Korea;Gwangju Institute of Science and Technology, Gwangju, Republic of Korea;Teleview, Sungnam-si, Kyunggi-do, Republic of Korea
Venue:
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Year:
2007

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Abstract

This paper proposes a parallel architecture of a parity checksum generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conventional serial processing architecture, leading to significant decrease in processing time for generating a parity checksum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.