A detailed cost model for concurrent use with hardware/software co-design
Proceedings of the 39th annual Design Automation Conference
Early estimation of the size of VHDL projects
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A First Step Towards Hw/Sw Partitioning of UML Specifications
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A priori implementation effort estimation for hardware design based on independent path analysis
EURASIP Journal on Embedded Systems - Operating System Support for Embedded Real-Time Applications
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
Application space exploration of a heterogeneous run-time configurable digital signal processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modifications to evaluate the cost-effectiveness of reusing VHDL-based designs, are presented. The proposed approach has been formalized using an approach similar to the COCOMO analysis strategy, enhanced by a project size prediction methodology based on a VHDL function point metric. The proposed design size estimation methodology has been validated through a significant benchmark, the LEON-1 microprocessor, whose VHDL description is of public domain