Processor customization for software implementation of the AES algorithm for wireless sensor networks

Authors:
Néstor Suárez;Gustavo M. Callicó;Roberto Sarmiento;Octavio Santana;Anteneh A. Abbo
Affiliations:
IUMA, Institute for Applied Microelectronics, ULPGC, University of Las Palmas of G.C., Spain;IUMA, Institute for Applied Microelectronics, ULPGC, University of Las Palmas of G.C., Spain;IUMA, Institute for Applied Microelectronics, ULPGC, University of Las Palmas of G.C., Spain;Philips Research Eindhoven, High Tech Campus, The Netherlands;Philips Research Eindhoven, High Tech Campus, The Netherlands
Venue:
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2009

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Abstract

The Advanced Encryption Algorithm (AES) has been the most widely used symmetric block cipher technique for providing security to applications adopting Wireless Sensor Networks (WSN). In this paper, an efficient software implementation of the AES algorithm is described running on an application specific processor (ASIP) platform that has been developed for use in low-power wireless sensor node designs with low memory requirements. Experimental results show that up to 46.3% reduction in cycle count is achievable through extensive code optimization. Hardware customization are proposed to the ASIP template to further improve the code performance. The gains include cycle count reductions of 33.1% and 45.2% for encryption and decryption, respectively and 21.6% reduction in code memory.