Efficient Software Implementation of AES on 32-Bit Platforms
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
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Proceedings of the 2004 ACM symposium on Applied computing
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CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
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FSE'05 Proceedings of the 12th international conference on Fast Software Encryption
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CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
FSE'10 Proceedings of the 17th international conference on Fast software encryption
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DaWaK'12 Proceedings of the 14th international conference on Data Warehousing and Knowledge Discovery
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WEWoRC'11 Proceedings of the 4th Western European conference on Research in Cryptology
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Image Communication
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This paper presents new speed records for AES software, taking advantage of (1) architecture-dependent reduction of instructions used to compute AES and (2) microarchitecture-dependent reduction of cycles used for those instructions. A wide variety of common CPU architectures--amd64, ppc32, sparcv9, and x86--are discussed in detail, along with several specific microarchitectures.