VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors

Authors:
Stefan Tillich;Johann Großschädl
Affiliations:
Graz University of Technology, Institute for Applied Information Processing and Communications, Inffeldgasse 16a, A---8010 Graz, Austria;Graz University of Technology, Institute for Applied Information Processing and Communications, Inffeldgasse 16a, A---8010 Graz, Austria
Venue:
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Year:
2007

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Abstract

Embedded systems require efficient yet flexible implementations of cryptographic primitives with a minimal impact on the overall cost of a device. In this paper we present the design of a functional unit (FU) for accelerating the execution of cryptographic software on 32-bit processors. The FU is basically a multiply-accumulate (MAC) unit able to perform multiplications and MAC operations on integers and binary polynomials. Polynomial arithmetic is a performance-critical building block of numerous cryptosystems using binary extension fields, including public-key primitives based on elliptic curves (e.g. ECDSA), symmetric ciphers (e.g. AES or Twofish), and hash functions (e.g. Whirlpool). We integrated the FU into the Leon2 SPARC V8 core and prototyped the extended processor in an FPGA. All operations provided by the FU are accessible to the programmer through custom instructions. Our results show that the FU allows to accelerate the execution of 128-bit AES by up to 78% compared to a conventional software implementation using only native SPARC V8 instructions. Moreover, the custom instructions reduce the code size by up to 87.4%. The FU increases the silicon area of the Leon2 core by just 8,352 gates and has almost no impact on its cycle time.