Montgomery Multiplication in GF(2^k
Designs, Codes and Cryptography
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Cryptography: Theory and Practice,Second Edition
Cryptography: Theory and Practice,Second Edition
Handbook of Applied Cryptography
Handbook of Applied Cryptography
A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
IEEE Transactions on Computers
Simplifying Quotient Determination in High-Radix Modular Multiplication
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
A Novel Unified Architecture for Public-Key Cryptography
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A unified architecture for a public key cryptographic coprocessor
Journal of Systems Architecture: the EUROMICRO Journal
VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A high-performance unified-field reconfigurable cryptographic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Recently, security in embedded system arises attentions because of modern electronic devices need cautiously either exchange or communicate with the sensitive data. Although security is classical research topic in worldwide communication, the researchers still face the problems of how to deal with these resource constraint devices and enhance the features of assurance and certification. Therefore, some computations of cryptographic algorithms are built on hardware platforms, such as field program gate arrays (FPGAs). The commonly used cryptographic algorithms for digital signature algorithm (DSA) are rivest-shamir-adleman (RSA) and elliptic curve cryptosystems (ECC) which based on the presumed difficulty of factoring large integers and the algebraic structure of elliptic curves over finite fields. Usually, RSA is computed over GF(p), and ECC is computed over GF(p) or GF(2 p ). Moreover, embedded applications need advance encryption standard (AES) algorithms to process encryption and decryption procedures. In order to reuse the hardware resources and meet the trade-off between area and performance, we proposed a new triple functional arithmetic unit for computing high radix RSA and ECC operations over GF(p) and GF(2 p ), which also can be extended to support AES operations. A new high radix signed digital (SD) adder has been proposed to eliminate the carry propagations over GF(p). The proposed unified design took up 28.7% less hardware resources than implementing RSA, ECC, and AES individually, and the experimental results show that our proposed architecture can achieve 141.8MHz using approximately 5.5k CLBs on Virtex-5 FPGA.