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Proceedings of the 2003 international symposium on Low power electronics and design
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Proceedings of the 2004 international symposium on Low power electronics and design
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Proceedings of the 33rd annual international symposium on Computer Architecture
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Low Power Methodology Manual: For System-on-Chip Design
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Many-core architectures provide a computation platform with high execution throughput, enabling them to efficiently execute workloads with a significant degree of thread-level parallelism. The burstlike nature of these workloads allows large power savings by power gating the idle cores. In addition, the load balancing of threads to cores also impacts the power and thermal behavior of the processor. Processor implementations of many-core architectures may choose to group several cores into clusters sharing the area overhead, so that the whole cluster is power gated as opposed to the individual cores. However, the potential for power savings is reduced due to the coarser level of power gating. In this paper, several hardware-based stateless load-balancing schemes are evaluated for these clustered homogeneous multicore architectures in terms of their power and thermal behavior. All these methods can be unified into a parameterized technique that dynamically adjusts to obtain the desired goal (lower power, higher performance, and lower hotspot temperature).