A cost-effective load-balancing policy for tile-based, massive multi-core packet processors
ACM Transactions on Embedded Computing Systems (TECS)
Hardware-based load balancing for massive multicore architectures implementing power gating
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power-thermal profiling of software applications
Microelectronics Journal
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In multi-core processors there are several ways to pair a thread to a particular core. These load-balancing techniques result in a quite different power, performance and thermal behavior of the processor, specially when low-power techniques like power gating are applied to the individual cores. In this work, a load-balancing technique that provides low overhead in performance and energy with respect to the highest performance case, yet featuring a smooth temperature distribution close to the optimal scenario is presented. An uneven temperature distribution leads to thermal hot spots which affect both the reliability of the processor (by stressing some parts of the die more than others), and the cost of the processor (since the package has to be designed to handle the worst hot spot).