New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology

Authors:
Koushik K. Das;Rajiv V. Joshi;Ching-Te Chuang;Peter W. Cook;Richard B. Brown
Affiliations:
University of Michigan, Ann Arbor, MI;IBM TJ Watson Research Center Yorktown Heights, NY;IBM TJ Watson Research Center Yorktown Heights, NY;IBM TJ Watson Research Center Yorktown Heights, NY;University of Michigan, Ann Arbor, MI
Venue:
Proceedings of the 2003 international symposium on Low power electronics and design
Year:
2003

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Abstract

This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed. A new method for assigning the VTH and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed. The optimum stacking height and tapering/sizing ratio under various design constraints are determined. Our strategies reduce MTCMOS standby leakage further by as much as 20X and reduce virtual supply noise by 15%.