Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power finite state machine synthesis using power-gating
Integration, the VLSI Journal
Stepwise sleep depth control for run-time leakage power saving
Proceedings of the great lakes symposium on VLSI
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Testing for SoCs with advanced static and dynamic power-management capabilities
Proceedings of the Conference on Design, Automation and Test in Europe
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Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This paper presents a tri-modal switch cell that enables implementation of multimodal power gating, including active, data-retentive drowsy, and deep sleep modes. A circuit realization and design methodology are presented that allow one to take advantage of the ultra low leakage deep sleep mode, low leakage, but very fast wakeup, drowsy mode, and an additional low leakage data-retentive mode. Experimental results demonstrate the benefits of this new switch and corresponding power gating technique.