Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis

  • Authors:
  • Sule Ozev;Alex Orailoglu

  • Affiliations:
  • -;-

  • Venue:
  • VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
  • Year:
  • 2002

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Abstract

Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize on-chip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.