Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Asymptotic probability extraction for non-normal distributions of circuit performance
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Hierarchical analysis of process variation for mixed-signal systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Effect of Process Variation on the Performance of Phase Frequency Detector
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
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RF circuits play a vital role in high data rate communication systems. Although at the design stage several considerations are made to ensure that the designed circuit functions as per desired specifications, the effect of process variations on the circuit's performance is less understood. The parametric variations arising from the various stages of fabrication play a significant role in determining the device characteristics. In this paper, in order to analyze the effect of process variations, we consider a bottom---up approach beginning at the component level for active and passive elements and then move to the circuit level in an RF circuit consisting of both analog and digital components. We take Low Noise Amplifier (LNA) and a Phase Frequency Detector (PFD) which is one of the important building blocks of a Phase Locked Loop (PLL) as case studies for circuit level analysis. In the case of LNA, the performance is analyzed in terms of the S-parameters, gain and Noise Factor on different topologies and for a PFD, an analytical model is developed and the analysis is carried out using the Monte Carlo method to verify the robustness of the circuit elements towards phase noise. Our hierarchical multi-phase analysis technique is shown to provide valuable insights into designing robust RF circuits.