On test generation for transition faults with minimized peak power dissipation
Proceedings of the 41st annual Design Automation Conference
Fault Diagnosis and Fault Model Aliasing
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Multiple-detect ATPG based on physical neighborhoods
Proceedings of the 43rd annual Design Automation Conference
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Non-uniform coverage by n-detection test sets
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We study the effectiveness of n-detection test sets based on transition faults in detecting defects that affect the timing behavior of a circuit. We use path delay faults as surrogates for unmodeled defects, and show that the path delay fault coverage achieved by an n-detection transition fault test set increases significantly as n is increased. We also introduce a method to reduce the number of tests included in an n-detection test set by using different values of n for different faults based on their potential effect on the defect coverage. The resulting test sets are referred to as variable n-detection test sets