Design of Partially Parallel Scan Chain

Authors:
Yoshinobu Higami;Kozo Kinoshita
Affiliations:
Department of Applied Physics, Osaka University;Department of Applied Physics, Osaka University
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

Citing 1
Cited 0

Configuring multiple scan chains for minimum test time

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a design-for-testability technique, called partially parallel scan chain ( PPSC ), which aims at reduction of test length for sequential circuits. Since the partially parallel scan chain allows to control and observe subset of flip-flops (FFs) concurrently during scan shift operations, the number of scan shift clocks is reduced.