An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
Analysis of Logic Circuits with Faults Using Input Signal Probabilities
IEEE Transactions on Computers
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
Fault-Tolerant Computing: A Introduction
IEEE Transactions on Computers
Power problems in VLSI circuit testing
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
| Hi-index | 14.98 |
It is shown that by a proper selection of the probabilities of 0 and 1 at the inputs, the efficiency of random test generation can be improved. This correspondence includes some results describing the testing of actual logic networks used in a computer.