Test data compression based on geometric shapes
Computers and Electrical Engineering
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Testing systems-on-a-chip (SOC) involves applying hugeamounts of test data, which is stored in the tester memoryand then transferred to the circuit under test (CUT) duringtest application. Therefore, practical techniques, such astest compression and compaction, are required to reduce theamount of test data in order to reduce both the total testingtime and the memory requirements for the tester. Relaxingtest sequences can improve the efficiency of both test compressionand test compaction. In addition, the relaxationprocess can identify self-initializing test sequences for synchronoussequential circuits. In this paper, we propose anefficient test relaxation technique for synchronous sequentialcircuits that maximizes the number of unspecified bitswhile maintaining the same fault coverage as the originaltest set.