Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
A polynomial-time algorithm for designing FIR filters withpower-of-two coefficients
IEEE Transactions on Signal Processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents the systematic synthesis of multiplier-less FIR filters with a novel complexity-aware quantization algorithm. Both signed-digit representations and common subexpression elimination (CSE) are investigated to reduce the computational complexity at the bit level. For comparable filter responses, the simulation shows that our approach requires only half (49.06%/spl sim/ 50.94%) additions of the straightforward quantized filters. Both with CSE, our FIR synthesizer has comparable results with the CSD-encoded coefficients, which have the theoretically minimum non-zero terms. Moreover, our approach outperforms CSD in most cases because of the direct control over additions and the zero-overhead insertion of non-zero terms.