Modern heuristic techniques for combinatorial problems
Modern heuristic techniques for combinatorial problems
Techniques for low power realization for FIR filters
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Low-power realization of FIR filters on programmable DSP's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
A New Architecture for Signed Radix-2m Pure Array Multipliers
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Proceedings of the 24th symposium on Integrated circuits and systems design
| Hi-index | 0.00 |
This paper proposes the implementation of Finite Impulse Response (FIR) filter architectures, whose the ordering and partitioning of the coefficients is based on heuristic algorithms. Due to the characteristics of the FIR filter algorithms, which involve multiplications of input data with appropriate coefficients, the best ordering and partitioning of these operations can contribute for the reduction of the switching activity, what leads to the minimization of power consumption in the filters. Thus, two algorithms were implemented for the ordering and partitioning of the coefficients and both of them are based on some heuristic approach. Low power array multipliers are used as basic modules for the implemented sequential and semi-parallel FIR filter architectures. As will be shown, the use of low power array multipliers with an appropriate choice of coefficients, based on the guidance given by the heuristic algorithms, can contribute for the reduction of power consumption of the FIR architectures.