Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters

Authors:
Mahesh Mehendale;S. D. Sherlekar;G. Venkatesh
Affiliations:
-;-;-
Venue:
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Year:
1998

Citing 0
Cited 2

Ordering and partitioning of coefficients based on heuristic algorithms for low power FIR filter realization

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Exploring the use of heuristic-based algorithms for the ordering and partitioning of coefficients for power efficient fir filters realization

Proceedings of the 24th symposium on Integrated circuits and systems design

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Abstract

We present algorithmic and architectural transforms for low power realization of Finite Impulse Response (FIR) filters implemented both in software on programmable DSPs and as hardwired macros. For the programmable DSP based implementation, these transform address power reduction in the program memory address and data busses and also the multiplier.We also propose architectural extensions to support some of these transformations. The transforms for hardwired FIR filters aim at reducing the supply voltage while maintaining the throughput. We also present transforms that reduce the computational complexity of the FIR filter computation and thus achieve power reduction.