Design of a radix-2m hybrid array multiplier using carry save adder format
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A new array architecture for signed multiplication using Gray encoded radix-2m operands
Integration, the VLSI Journal
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We present a new architecture for signed multiplication. The proposed architecture maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. We propose a Hybrid encoding for the architectures, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching characteristic of the Gray encoding. We have experimented using the Gray code foreach group of m bits, thus potentially further reducing the switching activity both internally and at the inputs. The architecture is extended for radix-2 m encoding, which leads to a reduction of the number of partial lines, enabling a significant improvement in performance and power consumption. The flexibility of our architecture allows for the easy construction of multipliers for different values of m. The results we present show that the proposed architecture with radix-4 compares favorably in performance and power with the Modified Booth multiplier.