Modified stable Euler-number algorithm implementation for real-time image binarization

Authors:
Naeem Abbasi;Jacques Athow;Aishy Amer
Affiliations:
Department of Electrical and Computer Engineering, Concordia University, QC, Canada H3G 2W1;Department of Electrical and Computer Engineering, Concordia University, QC, Canada H3G 2W1;Department of Electrical and Computer Engineering, Concordia University, QC, Canada H3G 2W1
Venue:
Journal of Real-Time Image Processing
Year:
2014

Citing 13
Cited 0

Image difference threshold strategies and shadow detection

BMVC '95 Proceedings of the 1995 British conference on Machine vision (Vol. 1)
Real-time thresholding with Euler numbers

Pattern Recognition Letters
Thresholding for Change Detection

ICCV '98 Proceedings of the Sixth International Conference on Computer Vision
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
Optimal binarization of images by neural networks for morphological analysis of ductile cast iron

Pattern Analysis & Applications
Embedded active vision system based on an FPGA architecture

EURASIP Journal on Embedded Systems
A new binarization algorithm based on maximum gradient of histogram

ICIG '07 Proceedings of the Fourth International Conference on Image and Graphics
Local Properties of Binary Images in Two Dimensions

IEEE Transactions on Computers
A parallel hardware architecture for connected component labeling based on fast label merging

ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
Digital image thresholding, based on topological stable-state

Pattern Recognition
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study

IEEE Transactions on Computers
Image change detection algorithms: a systematic survey

IEEE Transactions on Image Processing
A Co-processor for Computing the Euler Number of a Binary Image using Divide-and-Conquer Strategy

Fundamenta Informaticae

Quantified Score

Hi-index	0.00

Visualization

Abstract

The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In this paper a modified stable Euler-number-based algorithm for image binarization is proposed and its real-time hardware implementation in a Field Programmable Gate Array with a pipelined architecture is presented. The proposed modifications to the algorithm facilitate hardware implementation. The end result is a design that out-performs known software implementations. The amount of noisy pixels introduced during the binarization process is also minimized. Despite the stable Euler-number-based image binarization being computationally expensive, our simulations show that the proposed architecture gives accurate results and this in real time and without consuming all chip resources.