Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization

Authors:
Min Chu;David J. Allstot
Affiliations:
University of Washington, Seattle, WA;University of Washington, Seattle, WA
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

A hierarchical divide-and-conquer multi-optimization methodology for phase-locked loop synthesis is presented. By optimizing each building block in the PLL separately with various optimization techniques, high optimization efficiency and good circuit performance are achieved. The methodology is validated with the synthesis of a 1GHz third-order PLL in 240nm SiGe BiCMOS.