Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
High speed CMOS design styles
SOI circuit design concepts
Leakage-tolerant design techniques for high performance processors
Proceedings of the 2002 international symposium on Physical design
SOI Digital Circuits: Design Issues
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
| Hi-index | 0.00 |
Design guidelines for static and domino silicon-on-insulator (SOI) CMOS circuits are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-silicon. Most published design fixes for eliminating parasitic bipolar induced upset are shown to aggravate the charge sharing problem. A new and improved predischarge method for enhancing the noise tolerance of SOI domino circuits is thus proposed. The topic of multiple output domino logic in SOI technology is addressed for the first time. Multiple output domino logic is shown to be more prone to bipolar leakage induced upset than regular domino. Many of the design practices used to alleviate bipolar leakage in regular domino are no longer valid due to the multiple output domino logic's inherent design requirements. A novel SOI-specific multiple output domino logic, particularly suitable for adder designs, is introduced to minimize the bipolar leakage risk.