Critical evaluation of SOI design guidelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper reviews the recent advances in SOI digital CMOS circuits. Particular emphases is placed on the impact of floating-body in partially-depleted devices on the circuit operation, stability, and functionality. Unique SOI design aspects such as parasitic bipolar effect and hysteretic V_T variation are addressed. Circuit techniques to improve the noise immunity and global design issues are also addressed.