Closed-Form bounds for interconnect-aware minimum-delay gate sizing

Authors:
Giorgos Dimitrakopoulos;Dimitris Nikolos
Affiliations:
Technology and Computer Architecture Laboratory, Computer Engineering and Informatics Dept, University of Patras, Patras, Greece;Technology and Computer Architecture Laboratory, Computer Engineering and Informatics Dept, University of Patras, Patras, Greece
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit's performance and to increase designers' productivity. In this paper, we present a practical method to perform gate sizing, taking also into account the contribution of fixed wiring loads. Closed-form bounds are derived and a simple recursive procedure is developed that directly calculate the gate sizes required to achieve minimum delay. The designer, using the proposed method, can easily compare different implementations of the same circuit and explore the energy-delay design space, including in the analysis the effect of interconnect.